wafer.space Community - GitHub - SUD0NET/as16: 16-bit RISC CPU d...

10:46 p.m.

Very cool! Documentation of instruction format could use some improvement though. It took me a while to figure out that this architecture CAN in fact read memory, as the opcode is actually only 3 bits (not 4 like in the readme) and the top bit is actually the "read memory bit". Predicates aren't defined either, so I'm still a bit confused on what bits to set for the C/Z/Invert predicate bits to do something logical, or if there's a way to make an unconditional instruction.

10:48 p.m.

And if I'm correct the only way to branch is by writing to the PC register? Which combined with predicates instructions allows for conditional branching, nice

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10:51 p.m.

Also I think there's no way to add reg + reg, you can only add reg + imm or reg + mem?

1

documentation, indeed, needs improvement

11:52 p.m.

the opcode is actually 3-bit, as you stated

11:56 p.m.

but there is a modifier for the ADD/ADC mnemonics in line 35 of as16.v: ADD, ADC : {carry, result} = grf_dout + OR_q + (!IR_q[8] & C_q);

Though bit 8 is just one of the normal opcode bits, specifically the low bit that distinguishes between ADD and ADC. So still a 3-bit opcode

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kcolley

Though bit 8 is just one of the normal opcode bits, specifically the low bit that distinguishes between ADD and ADC. So still a 3-bit opcode

exactly.

Oh also it looks like you can only read and write to constant memory addresses? No array indexing or stack?

12:24 a.m.

Unless you do some self modifying code shenanigans, I guess...

kcolley

Oh also it looks like you can only read and write to constant memory addresses? No array indexing or stack?

well, EA_ED does let you add a reg to an offset to form an address...

Ah, missed that

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12:29 a.m.

I also don't see how sram is connected to anything in the core module. Seems unconnected?

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kcolley

I also don't see how sram is connected to anything in the core module. Seems unconnected?

exactly

12:30 a.m.

kinda just hardwired it outside from the cpu

So you're planning to use an external SRAM chip and ignore the internal SRAM you're generating?

kcolley

So you're planning to use an external SRAM chip and ignore the internal SRAM you're generating?

yep

12:31 a.m.

just going to treat the as16 as a microprocessor

12:31 a.m.

besides, i kinda rushed the design in those 3 days

Gotcha, yeah that was a very quick window haha

overall, i'm kinda happy for my first tapeout

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Yeah looks like it'll be a fun chip to play around with!

1:02 a.m.

congrats

kcolley

congrats

thx

1:12 a.m.

i'm not sure how i'm going to wirebond it

1:12 a.m.

as i didn't choose for COB packaging

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1:13 a.m.

i'll probably have to find some national facility to do it for me as an "academic institution"

hmm, I wonder if it would be feasible for WS to provide at least one CoB-packaged chip even if you elected to not have them all packaged. Could be really useful for initial testing, and I'd think it would logistically be not too difficult to do one extra CoB wirebonding per design. Main challenge would be to keep them separated without accidentally mixing them up I guess. cc @Tim 'mithro' Ansell for the idea

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kcolley

hmm, I wonder if it would be feasible for WS to provide at least one CoB-packaged chip even if you elected to not have them all packaged. Could be really useful for initial testing, and I'd think it would logistically be not too difficult to do one extra CoB wirebonding per design. Main challenge would be to keep them separated without accidentally mixing them up I guess. cc @Tim 'mithro' Ansell for the idea

fair enough

kcolley

hmm, I wonder if it would be feasible for WS to provide at least one CoB-packaged chip even if you elected to not have them all packaged. Could be really useful for initial testing, and I'd think it would logistically be not too difficult to do one extra CoB wirebonding per design. Main challenge would be to keep them separated without accidentally mixing them up I guess. cc @Tim 'mithro' Ansell for the idea

One of the biggest problem is the shipping costs and dealing with paperwork.

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ah, didn't think about the fact that it would require shipping to a separate facility for packaging, meaning that one chip would be a separate shipping expense...